ISSCC which is one of my favorite conferences is just over a week away! In anticipation I decided to follow up on a previous post where I proposed some Industry anecdotes regarding emerging memory from the ISSCC/IEDM programs (the chart titled “Emerging Memory References in IEDM/ISSCC”

This time, after some trial and error, I decided to focus on the terms “compute/* in memory”, “accelerator”, and “heterogeneous” as they represent what I believe is a tend in the conference and Industry in general. As shown in the “Frequency of Occurrence in ISSCC Program” chart, the occurrence of each of these terms has generally increased significantly over the eight year analysis period.

Why the apparent trend? I’m going to posit there are two significant factors behind it. The first is due to a true shift in Industry as Moore’s Law challenges and slowing become more and more problematic. Scaling hasn’t’ stopped, but as Moore’s Law (from a litho point of view) has slowed, architects and designers have turned to more “system” level solutions for optimization, with technologies like #chiplets and #CXL enabling a new set of heterogeneous capabilities, accelerator attach, and overall system optimizations. Compute-in-memory is another manifestation of this on the ML side of things. There is more and more work going into various memory technologies being used for analog multiply-accumulate, spiking-neuron functions, etc. This could enable a step-function in inference function density or power efficiency versus litho scaling.

Secondly, I suspect it is also a result of a conscious shift in focus by the ISSCC Program Committees. Occasionally a criticism has been leveled at the conference as being the “Chip Olympics” – it seemed to focus on papers presenting the “largest”, “fastest”, “most layers”, etc. This is a necessary aspect of the conference as it helps showcase the “state of technology”. That said, I know from my past tenure on one of these Committees that there is a deliberate attempt at balance – with both the “mostest” being considered, as well as work from academia, and with emergent technologies. There is also a real effort to include more “system focused” papers in the program. It’s still a “Circuits” conference – silicon is the norm; however, papers that also have in scope the higher level system above the chip were being encouraged.

With all this in mind, IMHO circuit designers as well as system architects and all between would find this conference educational and valuable, and if nothing else it’s a great opportunity to see and network with colleagues across Industry. I hope to see you there!