- 30+ yrs of Design & Project/Team Leadership
- JEDEC and CXL Board of Directors
- ASIC/FPGA/PCB Design History
- 20 Patents & Multiple Company/Industry Awards
- Experience in Individual and 30(b)(6) Testimony
Leveraging three decades of design, leadership, and technology experience to add value to clients through consulting in product strategy, emerging memory technologies, server interconnect and data center infrastructure, and highly effective Industry Standards/Consortium representation.
During his almost 14 years in Google’s Data Center Infrastructure Team, Rob served as a Technical Lead/Technologist for Memory Technology and Interconnect Standards, Technical Lead for the concept, design and deployment of Google’s first custom solid state storage infrastructure, and technologist for emerging memory technology tracking and engagement.
As part of an Advanced Technology Team, Rob was responsible for identifying potential emerging memory and interconnect technology partners and working to form collaborative relationships around these technologies via executive engagements, MOUs, Joint Developments, etc., and working with system architects and performance engineers to identify appropriate uses of these technologies in the data center infrastructure – model use cases, help build potential TCO (Total Cost of Ownership) models, and influence design optimizations at all levels of the server memory hierarchy. This work included evaluation of emerging interconnect standards such as Gen-Z , CCIX, and OpenCAPI. Rob served as Chairman for the OpenCAPI Enablement Work Group and on the CXL Board of Directors – participating in the formation of the organization from concept to incorporated industry consortium.
Other experience includes serving as Google’s primary JEDEC representative to various committees and task groups (JC40/42/45) and as the Google appointed director on the JEDEC Board of Directors.
Hands-on design experience at Google and before that with multiple years in the Automated Test industry (Teradyne, Megatest, LTX/Trillium) includes PCB, FPGA (Verilog) design, and ASIC design/synthesis as well as signal integrity and power delivery analysis.
LinkedIn Recommendations: https://www.linkedin.com/in/robsprinklehi/details/recommendations/